Shaik Sameera Bannu, S.Priyanka
Carry Adders, Register Transfer Level
Adders are the basic building blocks of many computational circuits. As a result, it is imperative to design fast adders and simultaneously optimize the power in these adders to the maximum extent possible. Carry Select Adder (CSA) is the most frequently used adder which works on the principle of pre computation of the sum and carry for each individual stage by assuming the carry in as ‘0’ and ‘1’. CSA employs additional Ripple Carry Adders (RCA) which induces an undesired increase in area as well as the delay as the carry is propagated through all stages. Thus the overall area and power consumption for CSA is also on the higher side. Hence, it is inevitable to opt for techniques to reduce the power consumption to achieve higher performance which is the eventual desired goal. This work involves Register Transfer Level design of 32-bit CSA with power and delay optimization techniques. The obtained results for the power consumed for each technique are hence analyzed and compared to obtain the best design which can be further implemented.
Article Details
Unique Paper ID: 145199

Publication Volume & Issue: Volume 4, Issue 7

Page(s): 622 - 629
Article Preview & Download

Share This Article

Join our RMS

Conference Alert

NCSEM 2024

National Conference on Sustainable Engineering and Management - 2024

Last Date: 15th March 2024

Call For Paper

Volume 11 Issue 1

Last Date for paper submitting for Latest Issue is 25 June 2024

About Us enables door in research by providing high quality research articles in open access market.

Send us any query related to your research on

Social Media

Google Verified Reviews