Implementation of high speed and energy efficient carry skip adder
Author(s):
Pranita R.Bujadkar, N N Gyanchandani
Keywords:
AOI,OAI,CSKA,RCA, PPA,CSLA
Abstract
In this paper we design carry skip adder for the purpose of lower energy consumption and it gives higher speed. The main function is that improves the delay, it is also known as carry bypass adder. The carry skip adder is that improves the delay of ripple carry adder with less effort compared with the other adder. Also the improvement in the worst-case delay is achieved by using various carry-skip adders to form a block-carry-skip adder. In this paper we shown that efficient carry skip adder in terms speed enhancement and it can be achieved by various method such as concatenation and increme ntation method. Also in addition, instead of using multiplexer logic, the proposed scheme makes use of AND OR Invert and OR AND Invert compound gate for the skip logic. AND OR Invert logic gates and AOI are basically two level compound logic functions constructed by or from the combination of one or more AND gates followed by a NOR gate. Also these gates can be easily implemented in CMOS circuitry. And or gates are particularly better than the total number of transistors or gate less than if the AND, NOT and OR functions were implemented separately. These results are in increased speed, reduced power, smaller area and potentially lower fabrication cost. And the results can be obtained by various tools such as Xilinx and Modesim 6.4b. Using this we can improves the delay on an average of 45% and the energy will be minimum 39%. Using CSKA we can achieve reduction power consumption compared with latest works in the field.
Article Details
Unique Paper ID: 145292

Publication Volume & Issue: Volume 4, Issue 8

Page(s): 407 - 414
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