DESIGN A LOW POWER SRAM ARCHITECTURE BASED ON FINFET TECHNOLOGY
Author(s):
J. PRAVEEN, B.PADMINI
Keywords:
Sram Architecture, Fintet
Abstract
Basically, the average 8T-SRAM does not need any write back scheme. But it has a competitive area. The average 8T SRAM architecture consists of full swing local bit line (BL). This bit line is connected to the gate of read buffer. This read buffer is obtained by boosted word line voltage (WL). The average 8T-SRAM is based on the advanced technology that is 22-nm FinFET technology. But in this 22 nm FinFET technology we do not use the word line voltage because it degrades the stability of SRAM. If it degrades the stability then gate of read buffer cannot exerts through the supply voltages then lager delays will occur in the SRAM. To overcome this differential SRAM technology is introduced. In this SRAM proposed architecture, by using cross coupled pMOSs the full swing of local bit lines are exerted and coming to the gate of read buffer, it exerts from a full vdd. This proposed SRAM architectures stores the multiple bits. Now this multiple bits examine from the minimum operating voltage and area per bit. Basically in one block this proposed SRAM stores four bits and obtains minimum voltage of 0.42v.Compared to the average-8T SRAM based on the 22-nm FinFET technology, the proposed SRAM architecture produces time delay less than 62.6.
Article Details
Unique Paper ID: 145034

Publication Volume & Issue: Volume 4, Issue 6

Page(s): 425 - 429
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