Reliable Low Power Multiplier Design Using Fixed Width Replica Redundancy Block

Reliable Low Power Multiplier Design Using Fixed Width Replica Redundancy Block
Author(s):
P.Tharani, R.Padmaja
Keywords:
Replica, Multiplier
Abstract
In this paper, we propose a reliable low-power multiplier design by adopting algorithmic noise tolerant (ANT) architecture with the fixed-width multiplier to build the reduced precision replica redundancy block (RPR). The proposed ANT architecture can meet the demand of high precision, low power consumption, and area efficiency. We design the fixed-width RPR with error compensation circuit via analyzing of probability and statistics. Using the partial product terms of input correction vector and minor input correction vector to lower the truncation errors, the hardware complexity of error compensation circuit can be simplified. In a 12 × 12 bit ANT multiplier, circuit area in our fixed-width RPR can be lowered by 44.55% and power consumption in our ANT design can be saved by 23% as compared with the state-of-art ANT design.
Article Details
Unique Paper ID: 144808 Publication Volume & Issue: Volume 4, Issue 4 Page(s): 91 - 100
Article Preview & Download

Share This Article

NCSST-2023

AICTE Sponsored National Conference on Smart Systems and Technologies

Last Date: 25th November 2023

LATEST INNOVATION’S AND FUTURE TRENDS IN MANAGEMENT

Last Date: 7th November 2023

IJIRT.org enables door in research by providing high quality research articles in open access market.

Send us any query related to your research on editor@ijirt.org