Simulation and Advantages of a Double Tail Comparator
Author(s):
Venkata Sai Rohit Bhagavatula
Keywords:
ADC, Cadence, Spice, 90nm
Abstract
Single tail comparators have higher input impedance. Due to the presence of high input resistance, the power consumed is low which results in less static power consumption. Moreover, it has no loss in voltage from VDD to ground which results in rail to rail output swing. But, it has only one path for the current to flow in the circuit and more number of transistors are present in the top half of the circuit which represents stacking and due to this high supply voltage is consumed for circuit operation. In order to overcome these limitations, Double tail comparator is considered.
Article Details
Unique Paper ID: 142763

Publication Volume & Issue: Volume 2, Issue 6

Page(s): 243 - 246
Article Preview & Download


Share This Article

Conference Alert

NCSST-2023

AICTE Sponsored National Conference on Smart Systems and Technologies

Last Date: 25th November 2023

SWEC- Management

LATEST INNOVATION’S AND FUTURE TRENDS IN MANAGEMENT

Last Date: 7th November 2023

Go To Issue



Call For Paper

Volume 10 Issue 1

Last Date for paper submitting for March Issue is 25 June 2023

About Us

IJIRT.org enables door in research by providing high quality research articles in open access market.

Send us any query related to your research on editor@ijirt.org

Social Media

Google Verified Reviews