CMOS Implementation of Low Complexity Multiplication Technique
Author(s):
Akanksha Goswami, Rajesh Bathija, shikha sharma
Keywords:
Complex multiplier, CMOS, DFT, FFT, Urdhva Tiryakbhyam Multiplier
Abstract
A low-complexity design for multiplication is primary requirement in Fast Fourier implementation. In this work an optimized multiplier for twiddle factor multiplier is designed. The proposed multiplier is slightly modified from the existing complex multipliers. A 3 bit multiplier is designed which results low power consumption with high speed. The presented complex multiplier with minimum complexity has with much less delay and simulation time, which reduces overall speed when implemented in FFT. The proposed CMOS implementation of multiplier is simulated in 45 nm scale using tanner tool version 14.11.
Article Details
Unique Paper ID: 142432

Publication Volume & Issue: Volume 2, Issue 1

Page(s): 336 - 338
Article Preview & Download


Share This Article

Conference Alert

NCSST-2021

AICTE Sponsored National Conference on Smart Systems and Technologies

Last Date: 25th November 2021

SWEC- Management

LATEST INNOVATION’S AND FUTURE TRENDS IN MANAGEMENT

Last Date: 7th November 2021

Go To Issue



Call For Paper

Volume 8 Issue 4

Last Date 25 September 2021

About Us

IJIRT.org enables door in research by providing high quality research articles in open access market.

Send us any query related to your research on editor@ijirt.org

Social Media

Google Verified Reviews

Contact Details

Telephone:6351679790
Email: editor@ijirt.org
Website: ijirt.org

Policies